1. Field of the Invention
The present invention relates to a detection of errors in data and, more particularly, to an error detector for detecting errors that occur in data under transmission.
The present invention relates to a semiconductor device comprising the error detector.
The present invention relates to an error detection method for detecting errors that occur in data under transmission.
2. Description of the Related Art
There are various factors which may cause errors in data being transmitted via transmission lines. For the detecting the errors, a transmitter in a communication system adds check data, under a given rule, to target data to be transmitted. A receiver in the communication system examines whether or not the transmitted data is in accordance with the rule and judges whether or not there are the presence of errors based on the result of the detection.
Out of error detection methods, the most prevalent one is a CRC (Cyclic Redundancy Check) method using a cyclic code. In the CRC error detection, the transmitter splits the target data to be transmitted into information bit strings of a specified length, represents each of the information bit strings in a polynomial, and divides it by a generator polynomial. The transmitter then generates the cyclic code by adding, as check bits, a remainder from the division to the information bit string and transmits the cyclic code to the receiver.
The receiver divides the received cyclic code by the same generator polynomial used at the transmitter to judge whether or not the presence of errors depending on whether or not the cyclic code is divisible.
FIG. 1 shows an exemplary communication system that performs the error detection by using the cyclic code. In the communication system, a transmitter 1, and a receiver 2 are connected to each other via a radio transmission line 3. The transmitter 1 and the receiver 2 correspond to, e.g., a base station and a mobile terminal for mobile communication such as a mobile phone, respectively.
The transmitter 1 has a coder 4 for coding data to be transmitted and a data modulating/transmitting unit 5 for modulating the coded data and outputting the modulated data to the radio transmission line 3. The coder 4 is composed of a feedback shift register 6.
The receiver 2 has a data receiving/demodulating unit 7 for receiving the data transmitted via the radio transmission line 3 and demodulating the received data, and an error detector 8 for detecting errors in the demodulated data. The error detector 8 is composed of a feedback shift register 9 and an right/wrong output unit 10 for outputting an error detecting signal FLAG. The error detector 8 has been formed in a semiconductor device SEM with other communication functional elements.
As shown in FIG. 2, the feedback shift register 6 and the feedback shift register 9 are composed of identical circuits such as dividers conforming to a sixteenth-degree generator polynomial X16+X12+X5+1.
Each of the feedback shift registers 6 and 9 has a register unit 11 consisting of flip-flop circuits X15 to X0 (hereinafter referred to as F/F circuits X15 to X0) connected in cascade, three EOR (Exclusive OR) circuits 12a, 12b, and 12c, and switches S1 and S2. In the register unit 11, a shift direction has been set such that data is shifted from the F/F circuit X0 to the F/F circuit X15. A clock signal CLK is connected to the clock terminal of each of the F/F circuits X15 to X0 such that shift operations are performed in synchronization.
The EOR circuit 12a receives an output of the F/F circuit X15 and an input signal DIN1 (or DIN2) and outputs the result of the operation to the F/F circuit X0. The EOR circuit 12b receives the output of the EOR circuit 12a and an output of the F/F circuit X11 and outputs the result of the operation to the F/F circuit X12. The EOR circuit 12c receives the output of the EOR circuit 12a and an output of the F/F circuit X4 and outputs the result of the operation to the F/F circuit X5.
The switch S1 is for selectively connecting the output of the F/F circuit X15 or the input signals DIN1 and DIN2 to the output signals DOUT1 and DOUT2 of the feedback shift registers 6 and 9. The switch 2 is for feeding back the output of the EOR circuit 12a to the EOR circuits 12b and 12c and to the F/F circuit X0.
In the communication system shown in FIG. 1, the transmitter 1 performs coding and the receiver 2 performs the error detection as follows. By way of example, the following description will be given to the case where a 6-bit information bit string “01 0101” is transmitted.
FIG. 3 shows the respective states of the F/F circuits X15 to X0 when the feedback shift register 6 at the transmitter 1 is operated. Upon each receipt of the clock signal CLK, the feedback shift register 6 shifts the values held by the F/F circuits X15 to X0 to the left in the drawing, so that “STATE” is incremented by 1 upon each receipt of the clock signal CLK. That is, the individual F/F circuits X15 to X0 undergo transitions from “STATE 0” to “STATE 6” when viewed in the columnar direction.
In “STATE 0”, each of the F/F circuits X15 to X0 is reset to “0”.
In “STATE 1” through “STATE 6” shown in FIG. 2, the switch S1 is switched to connect the input signal DIN1 to the output signal DOUT, and the switch 2 is closed. Consequently, the information bit string “01 0101” inputted from the input signal DIN1 is inputted to the feedback shift register 6 and outputted simultaneously to the output signal DOUT1.
The information bit string outputted to the output signal DOUT1 is modulated by the data modulating/transmitting unit 5 and then transmitted to the receiver 2 via the radio transmission line 3.
When the feedback shift register 6 has operated to reach “STATE 6”, the values “0100 0010 0001 0100” held by the respective F/F circuits X15 to X0 form a check bit string and the cyclic code “01 0101 0100 0010 0001 0100” enclosed in the bold rectangle of FIG. 3 are generated from the information bit string and the check bit string.
An output of the check bit string is performed by operating the feedback shift register 6 and sequentially outputting the values held by the F/F circuits X15 to X0 in “STATE 6” to the output signal DOUT1. At this time, the switch S1 is switched to connect the output of the F/F circuit X15 to the output signal DOUT1, and the switch S2 is open. By opening the switch S2, a “0” is inputted to each of the F/F circuit X0 and the EOR circuits 12b and 12c. 
The check bit string outputted to the output signal DOUT1 is modulated by the data modulating/transmitting unit 5 and then transmitted to the receiver 2 via the radio transmission line 3.
The data receiving/demodulating unit 7 at the receiver 2 receives the modulated cyclic code (information bit string +check bit string) and sequentially demodulates it to the original cyclic code. The data receiving/demodulating unit 7 inputs the individual bits of the cyclic code to the feedback shift register 9 of the error detector 8 in the order in which they were demodulated.
FIG. 4 shows the respective states of the individual F/F circuits X15 to X0 when the feedback shift register 9 of the error detector 8 is operated. It is to be noted that FIG. 4 shows the operation when the received cyclic code has no error.
In “STATE 0”, each of the F/F circuits X15 to X0 is reset to “0”. In “STATE 1” through “STATE 22”, the switch S2 of FIG. 2 is closed. The switch S1 may be switched to either side.
The feedback shift register 9 sequentially receives the cyclic code “01 0101 0100 0010 0001 0100” from the input signal DIN2. In “STATE 22” in which the cyclic code has been received up to the least significant bit (hereinafter referred to as LSB) thereof, the values held by the F/F circuits X15 to X0, i.e., the value of the remainder obtained by dividing the received cyclic code by the generator polynomial, is “0” when the received data is error-free.
Whether or not the remainder is “0” is verified by the right/wrong output unit 10 of FIG. 1. Therefore, the feedback shift register 9 sequentially outputs the values held by the F/F circuits X15 to X0 in “STATE 22” to the output signal DOUT2. At this time, the switch S1 is switched to connect the output of the F/F circuit X15 to the output signal DOUT2, while the switch S2 is open.
The right/wrong output unit 10 sequentially receives from the output signal DOUT2 a 16-bit value, which is the remainder from the division, performs a logical NOR operation with respect to each bit of the received value, and outputs the result of the operation to the error detecting signal FLAG. Accordingly, a “1” is outputted to the error detecting signal FLAG if the received cyclic code is correct. If the received cyclic code is erroneous, on the other hand, some of the values held by the F/F circuits X15 to X0 in “STATE 22” shown in FIG. 4 are nonzero. Therefore, a “0” is outputted to the error detecting signal FLAG as a result of the NOR operation performed with respect to each of the values held by the F/F circuits X15 to X0. If the error detecting signal FLAG is “0”, the receiver 2 discards the received data or gives a retransmission instruction to the transmitter 1.
By thus using the cyclic code, the communication system described above detects errors that have occurred on the data on the radio transmission line 3.
In general, communication systems perform not only the error detection but also the error correction for transmitted data. As an error correcting code for use in the error correction, a block code such as the cyclic code and a convolutional code are known. Since the radio transmission line used in mobile communication or the like has highly variable characteristics depending on geographical features and weather conditions and a burst error due to fading is likely to occur, the convolutional code effective in correcting the burst error is used frequently.
FIG. 5 shows an exemplary communication system that performs the error correction by using the convolutional code. In the communication system, the transmitter 1 has the coder 4, a convolutional coder 13, and the data modulating/transmitting unit 5 which are connected in series, and the receiver 2 has the data receiving/demodulating unit 7, a Viterbi decoder 14, a data processing unit 15, and the error detector 8 which are connected in series. In FIG. 5, the same components as used in FIG. 1 are designated by similar reference numerals.
In the communication system shown in FIG. 5, the detection and correction of errors in data transmitted from the transmitter 1 are performed at the receiver 2.
First, the coder 4 at the transmitter 1 obtains a check bit string from an information bit string to generate a cyclic code and sequentially outputs the cyclic code to the output signal DOUT1 having the information bit string side as the most significant bit (hereinafter referred to as MSB).
The convolutional coder 13 sequentially receives the cyclic code from the MSB side, generates the convolutional code, and outputs the code to the data modulating/transmitting unit 5. The data modulating/transmitting unit 5 modulates the convolutional code and outputs the modulated convolutional code onto the radio transmission line 3.
The data transmitting/demodulating unit 7 at the receiver 2 sequentially receives the modulated convolutional code, demodulates the code to the original convolutional code, and outputs it to the Viterbi decoder 14.
The Viterbi decoder 14 decodes the received convolutional code to the original cyclic code. During decoding, the Viterbi decoder corrects the burst error or the like that has occurred on the radio transmission line 3 to recover the original correct bit string. In the Viterbi decoder 14, the cyclic code is sequentially decoded from the LSB side and outputted.
Next, the cyclic code outputted from the LSB side is sequentially loaded into the data processing unit 15 and, after the reception is completed, the loaded cyclic code is outputted from the MSB side to the input signal DIN2 of the feedback shift register 9. Thereafter, the error detection is performed similarly to that performed by the communication system of FIG. 1 described above and the result of the detection is outputted as the error detecting signal FLAG.
To perform the error detection at the receiver 2 in the communication system shown in FIG. 1, all the bits of the cyclic code should be inputted bit by bit to the error detector 8. If the information bit string has considerable bit length, an increased processing time is required for the error detection, leading to the problem that the error detection process cannot be performed efficiently.
In the communication system shown in FIG. 5, the Viterbi decoder 1 at the receiver 2 decodes the cyclic code from the LSB side. The feedback shift register 9 receives the cyclic code from the MSB side to perform the error detection. Consequently, the receiver 2 cannot output the cyclic code sequentially decoded by the Viterbi decoder 14 directly to the feedback shift register 9.
As a result, the entire cyclic code should preliminarily be inputted from the LSB side to the data processing unit 15 and, after the decoding process by the Viterbi decoder 14 is completed, the cyclic code is finally outputted from the MSB side to the feedback shift register 9.
This causes the problems of the processing time extending from the decoding process to the error detection increasing and the circuit scale increasing.
The increased circuit scale further causes the problem that the chip size of the semiconductor device SEM increases when the error detector 8 has been formed into the semiconductor device SEM.
Since the error detection cannot be performed efficiently, there is the possibility that data transmission efficiency in the communication system is lowered.